Conventional systems utilizing a random access memory (RAM) (also referred to as a “system with RAM” or a “RAM employing system” in the present application), such as those including a dynamic random access memory (DRAM), typically have tight timing coupling, i.e., a known clock relationship, between the RAM and the RAM controller. In such systems having tight timing coupling, a single time domain exists between the RAM and the RAM controller, which allows the RAM controller to accurately track the status of the RAM on a per cycle basis to optimize the performance of the RAM. As such, the RAM controller can issue a sequence of RAM commands to the RAM in optimal order and with specific timing.
However, when conventional RAM employing systems are used with, for example, low-pin-count high performance systems, tight timing coupling between the RAM and the RAM controller may not be possible. More specifically, since low-pin-count high performance systems typically utilize buses that rely on flow control and loose timing coupling, the relationship between the clock of the RAM and the clock of the RAM controller will typically be unknown and difficult to determine. Therefore, in such systems utilizing loose timing coupling, a phase-shift results between the time domain of the RAM and the time domain of the RAM controller. Consequently, the specific timing of the RAM commands issued by the RAM controller to the RAM may not be maintained across the phase-shifted time domains, causing inaccurate or poor execution of RAM commands by the RAM.
Accordingly, there exists great need in the art for a RAM employing system that can be used with RAM controllers across multiple phase-shifted time domains, without sacrificing the RAM performance.